uc1827-1/-2 uc2827-1/-2 uc3827-1/-2 04/99 features ideal for multiple output and/or high voltage output voltage converters up to 500khz operation high voltage, high current floating driver for buck converter stage uc3827-1 current fed controller has push-pull drivers with overlapping conduction periods uc3827-2 voltage fed controller has push-pull drivers with non-overlapping conduction periods average current mode, peak current mode or voltage mode with input voltage feedforward control for buck power stage wide bandwidth, low offset, differential current sense amplifier precise short circuit current control buck current/voltage fed push-pull pwm controllers r d q s 20 delay 23 gnd 11 vcc ref 15 rt 17 ct 18 sync 19 csaC 9 csa+ 8 ss 4 csao 7 ceaC 13 veaC 16 vea+ 14 22 24 3 2 1 ramp cea+ 12 ceao veao 10 pull pgnd push src buck v+ delay delay t q q ref & uvlo ss inhbt uv osc 500khz max 6 5 21 current sense amplifier ilim comparator +3v current error amplifier pwm comparator 0.7v flying driver push-pull drivers osc uvlo voltage error amplifier block diagram description the uc3827 family of controller ics provides an integrated control solution for cascaded buck and push-pull converters. these converters are known as current fed or voltage fed push-pull converters and are ideally suited for multiple output and/or high voltage output applications. in both current fed and voltage fed modes, the push-pull switches are driven at 50% nominal duty cycles and at one half the switching frequency of the buck stage. in the current fed mode, the two switches are driven with a guaranteed over- lap period to prevent ringing and voltage stress on the devices. in the volt- age fed mode, the two switches are driven with a guaranteed gap time between the switches to prevent shorting the transformer across the en- ergy storage capacitor and to prohibit excessive currents flowing through the devices. the converters output voltage is regulated by pulse width modulation of the buck switch. the uc3827 contains complete protection and pwm con- trol functions for the buck converter. easy control of the floating switch is accomplished by the floating drive circuitry. the gate drive waveform is level shifted to support an input voltage up to 72vdc. (continued) udg-97172
2 uc1827-1/-2 uc2827-1/-2 uc3827-1/-2 gnd pgnd pull vcc ref delay sync ct push 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 src buck veao csao csaC ss ramp ceao v+ 10 11 12 csa+ cea+ ceaC rt veaC 15 14 13 vea+ connection diagrams dil-24 (top view) n or j, dw packages absolute maximum ratings supply voltage, vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v input voltage range for all pins except v+, buck, src . . . . . . . . . . C0.3v to 5v for v+ and buck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90v for src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90vCvcc buck driver io continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ma io peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a push/pull driver io continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200ma io peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a storage temperature . . . . . . . . . . . . . . . . . . . - 65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . C55c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . +300c voltages are referenced to ground. currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. plcc-28 (top view) q package the uc3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in current mode control. using current mode control prevents potential core saturation of the push-pull transformer due to mismatches in timing and in component tolerances. with average current mode control, precise control of the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak current mode control. the uc3827 average current mode loop can also be connected in parallel with the voltage regula- tion loop to assist only in fault conditions. other valuable features of the uc3827 include bidirectional synchronization capability, user programma- ble overlap time (uc3827-1), user programmable gap time (uc3827-2), a high bandwidth differential current sense amplifier, and soft start circuitry. description (cont.) uc 827 ordering information temperature range available packages uc1827-x C55c to +125c j uc2827-x C40c to +85c n, dw, q uc3827-x 0c to +70c n, dw, q temperature and package selection guide part number topology ucx827-1 current fed push-pull ucx827-2 voltage fed push-pull part version guide
3 uc1827-1/-2 uc2827-1/-2 uc3827-1/-2 electrical characteristics unless otherwise specified, vcc = 15v, v+ = 14.3v, ct = 340pf, rt = 10k, r delay = 24.3k, src = gnd, buck, push and pull outputs no load. t j = t a . parameter test conditions min typ max units supply vcc uvlo, turn-on 8.3 8.8 9.5 v hysteresis 0.9 1.2 1.5 v i vcc start vcc = 8v 1000 m a i vcc run 32 45 ma v+ uvlo, turn-on 7.1 7.5 8.3 v v+ hysteresis 0.2 0.4 0.9 v i v + buck high 0.2 1 2 ma voltage error amplifier ib 0.5 3 m a vio 10 mv avol 80 95 db gbw (note 7) 1 4 mhz vol i veao = 0 m a (no load) 0.3 0.5 v voh i veao = 0 m a (no load) 2.85 3 3.20 v current sense amplifier ib C1 C5 ua vio 5mv avol 80 110 db gbw (note 7) 15 29 mhz vol i ceao = 0 m a (no load) 0.25 0.5 v voh i ceao = 0 m a (no load) 3 3.3 v common mode range (note 7) 0 2 v current error amplifier ib C1 C5 m a vio 10 mv avol 80 110 db gbw at 100khz, measure gain 2 4.5 mhz vol i ceao = 0 m a (no load) 0.25 0.5 v voh i ceao = 0 m a (no load) 3.3 3.5 v common mode range (note 7) 0 5 v oscillator section frequency 180 220 250 khz ct discharge current 3.5v at ct when ct removed 5 ma pwm comparator minimum duty cycle 200khz 0 % maximum duty cycle 200khz 85 91 95 % buck output stage rise time 1nf load, (note 3) 40 100 ns fall time 1nf, load 30 80 ns voh i buck = C15ma , v+ Cbuck (note 4) 1.5 2.5 v i buck = C150ma, v+ C buck (note 4) 2 2.5 v vol i buck = 15ma (note 5) 0.2 0.4 v i buck = 150ma (note 5) 0.7 1.2 v
4 uc1827-1/-2 uc2827-1/-2 uc3827-1/-2 pin descriptions buck: output of the buck pwm controller. the buck output is a floating driver, optimized for controlling the gate of an n-channel mosfet. the peak sink and source currents are 1a. any undervoltage faults will dis- able buck to an off condition (low). cea+: the non-inverting input of the current error ampli- fier. ceaC: the inverting input of the current error amplifier. ceao: the output of the current error amplifier and the inverting input of the pwm comparator of the buck con- verter. csa+: the noninverting input of the current sense ampli- fier. csaC: the inverting input of the current sense amplifier. csao: the output of the current sense amplifier and the noninverting input of the current limit comparator. when the signal level on this pin exceeds the 3v threshold of the current limit comparator, the buck gate drive pulse is terminated. this feature is useful to implement cy- cle-by-cycle current limiting for the buck converter. ct: this pin is provided for the timing capacitor which is connected between ct and gnd. the oscillator fre- quency is set by ct and a resistor rt, connected be- tween pin rt and gnd. the ct discharge current is approximately 40x the bias current through the resistor connected to rt. a practical maximum value for the dis- charge current is 20ma. the frequency of the oscillator is given by: fosc = 0.77 rt ? ct electrical characteristics unless otherwise specified, vcc = 15v, v+ = 14.3v, ct = 340pf, rt = 10k, r delay = 24.3k, src = gnd, buck, push and pull outputs no load. t j = t a . parameter test conditions min typ max units push/pull output stages rise time 1nf load 50 100 ns fall time 1nf load 35 100 ns overlap time, -1 only 1nf loads (note 1) 100 250 400 ns non-overlapping time, -2 only (note 2) 100 250 500 ns voh i push/pull = C10ma, vcc C push (note 6) 2 3 v i push/pull = C100ma, vcc C push (note 6) 2.5 3 v vol i push/pull = 10ma (note 6) 0.2 0.8 v i push/pull = 100ma (note 6) 0.6 1.2 v reference ref voltage 4.8 5 5.2 v short circuit current ref = 0v C35 C50 C65 ma line regulation 9.5v < vcc < 20v 5 20 mv load regulation 0ma < io < 10ma 8 20 mv soft start vol, saturation vcc = 7v 250 500 mv i ss C5 C12 C25 m a note 1: the overlap time is measured from the point at which the rising edge of push/pull crosses 5v until the falling edge of pull/push crosses 5v. note 2: the non-overlap time is measured from the point at which the falling edge of push/pull crosses 5v until the rising edge of pull/push crosses 5v. note 3: measure the rise time from when buck crosses 1v until it crosses 9v. note 4: to force buck high, force csao=2.5v, ceao = 2.5v, a 25k pulldown resistor form ramp to ground, and ct = 0.5v. note 5: to force buck low, force csao = 2.5v, ceao = 2.5v, a 10k pulldown resistor from ramp to ground, and ct = 3.5v. note 6: to toggle push or pull into a desired state, pulse ct from 0.5v to 3.5v. push and pull toggle on the rising edge of ct. note 7: guaranteed by design. not 100% tested in production.
5 uc1827-1/-2 uc2827-1/-2 uc3827-1/-2 delay: a resistor to gnd programs the overlap time of the push and pull outputs of the uc3827-1 and the dead time of the push and pull outputs of the uc3827-2. the minimum value of the resistor, rdelay, is 18k w . the delay or overlap time is given by: tdelay = rdelay 200 ?10 sec. C9 w gnd: this pin is the ground reference for all sensitive setup components not related to driving the outputs. they include all timing, voltage sense, current sense, and bypass components. pgnd: ground connection for the push and pull out- puts. pgnd must be connected to gnd at a single point on the printed circuit board. this is imperative to prevent large, high frequency switching currents flowing through the ground metalization inside the ic. pull: ground referenced output to drive an n-channel mosfet. the pull and the push outputs are driving the two switches of the push-pull converter with comple- mentary signals at close to a 50% duty cycle. any undervoltage faults will disable pull to an off condition (low). push: ground referenced output to drive an n-channel mosfet. the pull and the push outputs are driving the two switches of the push-pull converter with comple- mentary signals at close to a 50% duty cycle. any undervoltage faults will disable push to an off condition (low). ramp: the ramp voltage, after a 700mv internal level shift, is fed to the noninverting input of the buck pwm comparator. a resistor to vin and a capacitor to gnd pro- vide an input voltage feedforward signal for the buck con- troller in voltage mode control. in peak current mode control, the ramp pin receives the current signal of the buck converter. in an average current mode setup, the ramp pin has a linearly increasing ramp signal. this waveform may be generated either by connecting ramp directly to ct, or by connecting both a resistor from vcc to ramp and a capacitor from ramp to gnd. ref: the output of the +5v on board reference. bypass this pin with a capacitor to gnd. the reference is off when the chip is in undervoltage lockout mode. rt: a resistor to gnd programs the charge current of the timing capacitor connected to ct. the charge current ap- proximately equals: ref 2? rt the charge current should be less than 500 m atokeep cts discharge peak current less than 20ma, which is cts maximum practical discharge value. the discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge current. src: the source connection for the floating buck switch. the voltage on the src pin can exceed vcc but must be lower than 90v-vcc. also, during turn-off transients of the buck switch, the voltage at src can go to C2v. ss: the soft start pin requires a capacitor to gnd. dur- ing soft start the output of the voltage error amplifier is clamped to the soft start capacitor voltage which is slowly charged by an internal current source. in uvlo, ss is held low. sync: sync is a bidirectional pin for the oscillator. this pin can be used to synchronize several chips to the fast- est oscillator. its input synchronization threshold is 1.4v. the sync voltage is 3.6v when the oscillator capacitor, ct, is discharged. otherwise it is 0v. if the recommended synchronization circuit is not used, a 1k or lower value resistor from sync to gnd may be needed to increase the fall time of the signal at sync. vcc: a voltage source connected to this pin supplies the power for the uc3827. it is recommended to bypass this pin to both gnd and pgnd ground connections with good quality high frequency capacitors. vea+: the non-inverting input of the voltage error ampli- fier. veaC: the inverting input of the voltage error amplifier. veao: the output of the voltage error amplifier. v+: supply voltage for the buck output. the floating driver of the uc3827 uses the bootstrap technique which re- quires a reservoir capacitor to store the required energy for the on time of the buck switch. a diode must be con- nected from vcc to v+ to charge the reservoir capacitor. this diode must be able to withstand vin. the reservoir capacitor must be connected between v+ and src and its voltage is monitored directly by the undervoltage lock- out circuitry of the buck driver. pin descriptions (cont.)
6 uc1827-1/-2 uc2827-1/-2 uc3827-1/-2 + C v ref 2.5v v ref 1.4v 2.5v 2.9v 0.5v 10k rt ct sync r t c t oscillator s r figure 1. oscillator block with external connections. application information pwm oscillator. the oscillator block diagram with exter- nal connections is shown in fig. 1. a resistor (r t ) con- nected to pin rt sets the linear charge current: i v r rt t ? 25 . the timing capacitor (c t ) is linearly charged with the charge current forcing the osc pin to charge to a 3.4v threshold. after exceeding this threshold, the rs flip-flop is set driving clksyn high and rdead low which dis- charges c t . ct continues to discharge until it reaches a 0.5v threshold and resets the rs flip-flop which repeats the charging sequence as shown in fig. 2. as shown in fig. 3, several oscillators are synchronized to the highest free running frequency by connecting 100pf capacitors in series with each clksyn pin and connect- ing the other side of the capacitors together forming the clksyn bus. the clksyn bus is then pulled down to ground with a resistance of approximately 10k. referring to fig. 1, the synchronization threshold is 1.4v. the oscil- lator blanks any synchronization pulse that occurs when osc is below 2.5v. this allows units, once they discharge below 2.5v, to continue through the current discharge and subsequent charge cycles whether or not other units on the clksyn bus are still synchronizing. this requires the frequency of all free running oscillators to be within 17% of each other to guarantee synchronization. circuit block description 100pf sync 100pf sync 100pf sync 100pf sync 10k clksyn bus osc1 osc2 osc3 osc10 figure 3. oscillator synchronization connection diagram. osc clksyn out vao current command 2.9v 0.5v 3.6v 1.4v 8.5v 0v threshold charging discharging figure 2. oscillator and pwm output waveform. udg-99085 udg-99087 udg-99086 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 ? fax (603) 424-3460
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
|
